发明名称 BUFFER CIRCUIT
摘要 PURPOSE:To obtain an address buffer circuit which works at a high speed with a small amount of power consumption, by setting the precharging level of the output of a preamplifier less than the prescribed value. CONSTITUTION:A preamplifier III forming an address buffer circuit together with a main amplifier IV contains connecting parts V and VI for transistors TRT1- T3, TRT4-T6, etc. Then an output A' and an anti-output A' of the amplifier III have operations from VDD-3VT, where VDD is the power supply voltage and VT is the threshold voltage of a transistor. Thus the working speed is accelerated with a low precharging level compared with a case when a unit of TR is used to start an operation from VDD-VT. Owing to this low precharging level and high-speed operation, the current flowing through TRQ27, Q26 and Q25 as well as TRQ27, Q30 and Q29 of the amplifier IV is reduced. This realizes an address buffer circuit which has a high-speed operation with a small amount of power consumption.
申请公布号 JPS58121196(A) 申请公布日期 1983.07.19
申请号 JP19820003795 申请日期 1982.01.13
申请人 NIPPON DENKI KK 发明人 KANEKO SHIYOUJI
分类号 G11C11/413;G11C8/06 主分类号 G11C11/413
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