| 摘要 |
PURPOSE:To simplify the circuit constitution in free response to the clock time, by constituting a binary frequency division circuit with >=2 stages of FFs in cascade connection and applying either an output of a master or a slave station or an inverted output to an input of an arbitrary FF. CONSTITUTION:A plurality of master slave type FF2, in cascade connection of >=2 stages and a differentiating circuit 1 form a binary frequency division circuit. A clock is inputted to an input C0 of the master FFs 2, the output -Q0 is applied to an input D0, the outputs -Q1, -Q2 are inputted to data inputs D1, D2 and a clock start signal RST is applied to preset inputs R0-R2 of each FF2. Further, the combination of output signals T10-T21 of outputs QM0-QM2, -QM0--QM2, Q0-Q2, and -Q0--Q2 of each FF2 is inputted to the inputs C1, C2 of the slave FF2. The frequency dividing ratio is selected freely in response to the clock time to simply the circuit constitution. |
