| 摘要 |
A monolithically very large scale integrated circuit (VLSI) having any arbitrarily given structure and an internal test circuit only requiring one, two or three additional outer terminals wherein the test circuit is integrated therein. In one embodiment the test circuit contains a counter and a combinational circuit interconnected with the counter reading outputs thereof as well as selection switches associated with test points and where the first of the additional terminals is connected to the counting input of the counter. |
