| 摘要 |
PURPOSE:To considerably simplify the circuit configuration of a local memory controlling section of each device, by accessing a memory by an address selected by an appropriate switching circuit on plural devices. CONSTITUTION:A refresh counter 5 outputs a refresh address RAD and a refresh request RRQ onto a bus 12' a clock timing from a clock source 6. The refresh address RAD and the refresh request RRQ outputted onto the bus 12' are inputted into a CPU8, main storing device 9, multiplexer 3 and a conpetition judging circuit 4 of the memory controlling circuit 12 of channels 10 and 11. The competition judging circuit 4 of the circuit 12 executes the memory (DM) at each timing refresh depending on the existence of the access request ARQ of each device to local memories 7a-7d. |
