| 摘要 |
PURPOSE:To obtain invariably phase-locked clock pulses by performing an automatic phase adjustment of clock pulses generated in correspondence to the phase of respective information bits of a transmitted information signal. CONSTITUTION:When supplied with a character signal CS, an edge detecting circuit 1 generates sampling pulses SP synchronizing with edges of respective information bits of the signal CS. Those pulses SP are supplied to an FF10 to decide on phase relation with the clock pulses SP outputted from a shift register 16. If the signal CS leads in phase and the pulses CP lag in phase, the output Q of the FF circuit 10 goes up to a level H and an up/down counter 11 is placed in up mode. Consequently, every time the pulse CP is generated, the counter 11 counts up successively and every time its counted value increases by one, the period of a shift clock SC generated by a shift clock generating circuit 12 is shortened. Consequently, the phase of the pulses CP generated by the register 16 is advanced. |
