发明名称 LEVEL CONTROL SYSTEM
摘要 <p>PURPOSE:To make time corrections among processes of respective levels positively and to perform various processes effectively, by performing a low-level process successively after the completion of the last process when the low level processes of an electronic exchange system extend over >=2 clocks. CONSTITUTION:Exchange processes of the electronic exchange system are classfied by a level H at which processes are carried out periodically without delay, a level L at which delay is permitted to some extent, and a base level, and those levels are given priority respectively to perform the processes according to programs in a main memory MM. A control part CONT connected to the memory MM accepts a clock interruption to drive high-level and low-level timers CHT MR and CLTMR through H-level and L-level driving circuits INC1 and INC2, and an arithmetic circuit OP makes a comparison. When an L-level clock repeats more than twice, a next L-level process is carried out successively after the process to make time connections of process times of respective levels.</p>
申请公布号 JPS58116893(A) 申请公布日期 1983.07.12
申请号 JP19810214810 申请日期 1981.12.29
申请人 FUJITSU KK 发明人 YAMADA MIKIO;SAKAGAMI KENJI
分类号 G06F1/14;G06F9/48;H04Q3/545 主分类号 G06F1/14
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