发明名称 EXCHANGE CONTROL SYSTEM
摘要 PURPOSE:To offer an exchange control system for a multi-processor unit system which can connect many line control systems efficiently, without remarkable reconstruction of the hardware, by providing a virtual input/output buffer memory for a common memory. CONSTITUTION:An ROW called from a line A is picked up from an IB0 by a CPU0 for call reception processing. Assuming that a called party X recognizes to be connected with a line B of a CCU1. The CPU0 rewrites a TSN-CPU No conversion table 43 provided corresponding to a TSN (channel address) of the line B so that it is indicated that the TSN on the line B is controlled with the CPU0. Further, the CPU0 sets an ORW for the start to the line B to a block on a virtual OB42 corresponding to the CCU1. The CPU1 monitors whether or not the ORW exists in the block corresponding to the CCU1 on the virtal OB42 periodically, and when exiting, the ORW is copied to the block corresponding to the IMOB42 on an MM. The CPU1 picks up the ORW copied from the IMOB42 with the IB/OB switching instruction from the CPU1 and controls the start of the line B.
申请公布号 JPS58115958(A) 申请公布日期 1983.07.09
申请号 JP19810211400 申请日期 1981.12.29
申请人 FUJITSU KK 发明人 OOYAMA MOTOMU;AIDA SOUICHIROU;IWABUCHI EISUKE
分类号 H04Q3/545;H04L12/50;H04Q11/04 主分类号 H04Q3/545
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