| 摘要 |
PURPOSE:To prevent the malfunction of the system due to the function fault or the like of a channel device, by providing a circuit, which inhibits other devices from using a bus during the memory access time of a device to which a bus use permission signal is given, in a bus controlling part. CONSTITUTION:When channel CH devices 5a-5z output direct memory access DMA request signals DMARQ to a bus controlling part 2 through a common bus 4, the controlling part 2 inputs these signals to a priority level encoder and selects a signal having a preliminarily set highest priority level from signals DMARQ and outputs this signal to a decoder. The decoder outputs level 1 to only the FF which outputs a permission signal DMAA0 corresponding to this selected signal number. A bus controlling right is given to the CH device to which the signal DMAA0 is given, and an address signal, a read/write signal, a strobe signal, etc. to a memory 3 are outputted to the bus 4 to access the memory 3. The controlling part 2 transmits the signal DMAA0 continuously during the memory access time of the CH device to inhibit other CH devices from using the bus by an NAND gate. |
