发明名称 MEMORY BOARD TEST SYSTEM
摘要 PURPOSE:To detect easily a fault of a block address decoder incorporated in a memory board during its test by adding a block address to be supplied to the block address decoder to part of test data when writing the test data in a memory. CONSTITUTION:In an initial write cycle, addresses of blocks A-D of the memory board are (000), (001), (010), and (011). When the block address (000) is applied to the memory board 3, the block A is selected to write test write data in its memory chip. In a read cycle, the host three digit bits are replaced for the block address (000) by a data selector 5. Therefore, when normal write data including the block address of the block A is read out of the memory board 3, a comparator 6 generates a coincidence output. If, however, the decoder malfunctions to select a wrong block, the block address in read data is different from the address (000) of the block A and the comparator 6 geneates a dissidence signal indicating an error.
申请公布号 JPS58115699(A) 申请公布日期 1983.07.09
申请号 JP19810215496 申请日期 1981.12.28
申请人 FUJITSU KK 发明人 HAMADA TAKASHI;MATSUBARA SATOSHI
分类号 G06F12/16;G11C29/08 主分类号 G06F12/16
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