发明名称 DECODER CIRCUIT
摘要 PURPOSE:To supply a steady current only to a decoder that is being selected, by using a predecoder containing a logical circuit consisting of transistors of parallel and series connections to control the connection of power supply between said predecoder and a main decoder. CONSTITUTION:The output of an NOR circuit NOR1 in which n channel enhancement type transistors TRQc1, Qc2- of a predecoder PD are connected in parallel is inverted to a low level when at least one of address bits AO, A1- is set at a high level in a non-selection state. Therefore a TRQd2 having the same structure as TRQc1, etc. of a main decoder MDC is turned off via a TRQO. Thus no steady current is supplied to the decoder MDC from a power supply B. One of the other hand, one of TRQa1, Qa2- which form an AND circuit AND 1 of the decoder PDC and is controlled with an inverted address bit is turned off. Therefore no steady current is supplied to the decorder PDC. As a result, the current is supplied only to a decoder in a selection state. This can save the power consumption.
申请公布号 JPS58114390(A) 申请公布日期 1983.07.07
申请号 JP19810210536 申请日期 1981.12.26
申请人 FUJITSU KK 发明人 SHINOKI TOORU
分类号 G11C11/413;G11C8/10 主分类号 G11C11/413
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