| 摘要 |
PURPOSE:To read output data of a designated low-speed input part without lowering the operation speed of a controlling part, by providing a high-speed bus buffer and a selecting register between the controlling part and each low- speed input part. CONSTITUTION:A device address signal from a controlling part 2 of a low-speed input controller is applied to a selecting register 8 to select plural low-speed input parts 1a-1i. One of input parts 1a-1i selected by the address signal is activated, and output data is held on a low-speed input data bus 6. Next, a high- speed bus buffer part 5 is activiated by the controlling part 2, and data on the data bus 6 is put onto a bidirectional high-speed data bus 7 by the buffer part 5 and is transmitted to the controlling part 2. Thus, output data from plural input parts 1a-1i are read without lowering the operation speed of the controlling part 2 and generating the bus contention. |
