| 摘要 |
PURPOSE:To drop the potential of a bit line sufficiently, to prevent malfunction and to obtain the dynamic gain memory cell having the high degree of integration by connecting the gate and drain of an MISFET and unifying a data line and the bit line. CONSTITUTION:A JFET Q3 uses a layer 17 as a floating gate and is capacitive- coupled with the gate 41 connected in common with the drain 16 through the capacitance C1 of a SiO2 film 12, a buried channel FET with a junction floating gate is constituted in a section Q3', conventional data lines are unnecessitaed, and the degree of integration can be improved. A Q4 (a section 61) is a taperd gate element having small output voltage difference, and uses the layer 17 as a source, a layer 14 as a back gate, a substrate 11 as a drain and the layer 41 as a gate. To connect the bit line 41 and the drain, a gate insulating film 12 is bored and the electrode 41 is formed, a source 15 is formed through self-alignment, and a word line 22 is connected. According to such constitution, a cell array having high density is formed, the magnitude of the forward rise voltage of a diode is detected and ''1'' or ''0'' is discriminated, and the memory cell resulting in no defective reading is obtained. |
