| 摘要 |
<p>PURPOSE:To suppress the increase in an amount of interference between codes, and to improve the timing characteristics, by inserting the complementary code just before the pulse or before several bits to the m-th bit of a binary signal series, and suppressing the consecution of the same codes. CONSTITUTION:A binary signal inputted to a binary signal input terminal 1 is synchronized with a clock at a 1-bit shift register 4 and outputted to Q,-Q terminals. Further, the clock is frequency-divided at a 1/m frequency division circuit 5 and converted into a clock pulse CM. An AND between the clock pulse CM and the output of the Q and -Q terminals is produced at reset, set pulse generating sections 6, 7, to form a control signal for the reset and set pulses. The control pulse is shifted for 2-bit's share at bit shift registers 9, 10. The binary signal series compensating the delay time of the operation at a phase adjusting gate circuit 8 is outputted from an output terminal 3 through set or reset control at each m-bit.</p> |
