发明名称 TOTAL ADDER
摘要 PURPOSE:To constitute a simple circuit whose number of elements is small, by forming a voltage signal of quarternary by adding 3 inputs of a current of binary, comparing this quarternary with 2 reference voltages, and forming a sum signal and a carry signal. CONSTITUTION:3 current inputs A, B and Ci of the same value are supplied to a resistance R1 and are converted to voltage, and 4 voltage signals V0-V3 are formed in an adder 11. This signal is applied to the base of a transistor TRT1 and T5 for forming a differential switch of voltage comparators 12, 13. A reference voltage generating circuit 14 is constituted of a resistance R2, a TRT3 and a DC power supply Va, and applies reference voltage to a TRT2 and T4 for forming the differential switch of the voltage comparator 12, 13. When all current inputs are off and the voltage signal is V0, a sum signal S and a carry signal C0 turn off, and when a current input is one and voltage is V1, the sum signal S is outputted, and when the inputs are two and voltage is V2, the carry signal C0 is outputted, and when all the inputs are turned on and voltage is V3, the sum signal S and the carry signal C0 are outputted. In this way, the circuit configuration is simplified.
申请公布号 JPS58114238(A) 申请公布日期 1983.07.07
申请号 JP19810212916 申请日期 1981.12.28
申请人 MATSUSHITA DENKI SANGYO KK 发明人 AONO KUNITOSHI;MORI TOSHIKI;YAMADA HARUYASU;HASEGAWA KENICHI;SHIBATA ATSUSHI
分类号 G06F7/501;G06F7/50;G06J1/00;H03K19/0175 主分类号 G06F7/501
代理机构 代理人
主权项
地址