发明名称 DYNAMIC GAIN TYPE SEMICONDUCTOR MEMORY
摘要 PURPOSE:To obtain the dynamic gain type memory having large output voltage difference by forming a second MIS gate electrode between the substrate of a threshold variable type buried channel MIS transistor and a first MIS gate electrode through an insulating layer. CONSTITUTION:The poly Si gate electrode 11 is buried into a SiO2 thick-film 13 on a P-type Si substrate 6, N layers 14, 15 are formed through double diffusion through a gate oxide film by masks 11, and the buried channel transistor 16 is formed. An MOSFET using the N layer 14 as a base body and a surface P type inversion layer as a channel is formed at the same time. The second gate electrode 12 in Mo is shaped. The voltage of the floating gate 15 is determined by the ratio C1/(Cj+C1) of junction depletion-layer capacitance Cj between the gate 15 and the channel 14 to capacitance C1 between the gate 15 and a control gate (a data line) at that time, and the dynamic gain cell having the large voltage difference of output to prescribed gate voltage of a writing control transistor is obtained.
申请公布号 JPS58114450(A) 申请公布日期 1983.07.07
申请号 JP19810209759 申请日期 1981.12.28
申请人 FUJITSU KK 发明人 TAGUCHI MASAO
分类号 G11C11/401;H01L21/8242;H01L27/108;H01L29/78 主分类号 G11C11/401
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