| 摘要 |
An integrated circuit memory cell pair having its data lines insulatively disposed from the semiconductor substrate at all points other than the point of electrical contact to the transistors of each memory cell. The semiconductor substrate has drain and source regions about the transmission channel of the field effect transistor and has a first capacitor electrode integral with one terminal of the transistor. A first polysilicon layer insulatively disposed from the substrate provides a conductive layer for a second capacitor electrode for each memory cell. A second insulatively disposed polysilicon layer provides the gate regions of the transistors and the data lines. The data lines make electrical contact through a self-aligned buried contact. Using this construction, a highly dense memory cell array is achieved without sacrificing capacitor area.
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