MULTI-INPUT SIGNAL COMPARATOR

摘要

PURPOSE:To realize an application of a multi-input signal comparator to a processor of various types of data which requires a fail-safe function, by detecting quickly the discordance after giving a comparison to the data signals of two systems and plural bits. CONSTITUTION:A data of ''1'' is set previously to a front stage SF by a presetting circuit, and therefore the shifts from the rear stage SR from the stage SF and vice versa are repeated in response to the shift pulses (f) and (g). Then an output (j) is obtained from the stage SR. This output (j) is delayed by a delaying circuit DL to be converted into an output (k) and then applied to the 2nd shift register SRG2 in the form of a control pulse. Then a shift from the stage SF to SR and vice versa are carried out when the output (k) is ''1'' and ''0'', respectively. An amplifying detector AD is connected to the output side of the rear stage of the register SRG2 in order to actuate a relay RL.