| 摘要 |
PURPOSE:To measure channel concentration of the semiconductor at the vertical JFET by a method wherein the voltage value of a reverse voltage between gates and a drain to generate a rapid variation of electrostatic capacity and channel size between the gates obtained according to a grinding means are used. CONSTITUTION:The P<+> type layers 9 are buried in an N type Si substrate 1 having concentration ND preventing mutual contact by N type compensation layers 7, 7', and an N type epitaxial layer having concentration NE is stacked thereon. The N type of the layers 7, 7' is canceled by B ions diffused from the P<+> type layers 9 according to thermal diffusion, and concentration of the channel 5' is reduced. When reverse voltages V are applied between the drain 3 and the cylindrical gates 9, before (A1) and after (A3) generation of the pinch off condition of depletion layers 6, capacity C varies rapidly at V=qNDb<2>/2epsilon. At this time, V=1 and epsilon, q are known. Then the element is ground at an angle and is colored, and when channel size is measured, channel size becomes to 2b. When b is decided as b 3mu, concentration ND of the channel can be calculated from the above-mentioned expression. |
