| 摘要 |
PURPOSE:To obtain an ECL (Emitter Coupled Logic) type delay circuit having increased delay time by equipping an ECL circuit with a transistor (TR) which operates in a saturation area. CONSTITUTION:For example, input terminals IN1 and IN2 are at a level L. Then, TRs Q1 and Q2 are tuned off, a TRQ6 is turned on, and a reference-side TRQ3 is turned on. Therefore, a current flows from a VCC to a VEE through an R4, Q6, etc., and the collector potential of the TRQ6 is at the level L. Further, the TRQ6 when turning on operates in a saturation area, so if either one of the input terminals IN1 and IN2 goes down to a level H, the TR Q1 or Q2 turns on, so that even if the TRQ3 turns off, the base potential of the TRQ6 does not go down to the level L immediately. After the collector-base stored charge of the TRQ6 is discharged through the TRs Q1 and Q2, the base potential of the TRQ6 falls to the level L firstly. This variation is obtained as L-to-H level variation at an output terminal OUT through an emitter follower TRQ5. |
