| 摘要 |
<p>An address generator responsible to input parameters for generating addresses to read out the content of a memory along parallel lines disposed at an angle to the orthogonal rows and columns of storage elements. The address generator has a first pair of registers (100, 116) coupled by an adder (108) to generate line corrected X addresses, a second pair of registers (102, 118) coupled by an adder (110) for generating first address corrections, an adder (124) summing said line corrected X addresses with said first address corrections to generate X addresses, a third pair of registers (104, 120) coupled by an adder (112) to generate line corrected Y addresses, a fourth pair of registers (106, 122) coupled by an adder (114) to generate second address corrections, and an adder (126) summing said line corrected Y addresses with said second address corrections to generate Y addresses.</p> |
