发明名称 ANALOG OUTPUT CIRCUIT
摘要 PURPOSE:To attain an analog output corresponding to a failure of a CPU, by detecting the absence of a clock signal at a detecting circuit, resetting a register for data signal and making all parts of a gate circuit for location selecting signal high in level. CONSTITUTION:In a detection circuit 8, each time a clock signal comes from a CPU1, a transistor (TR) turns on and charges charged in a capacitor C' are discharged. When a CPU1 is failed due to a failure, the clock signal is not given to the circuit 8, the charges in the capacitor C' are not discharged and when the potential exceeds a prescribed level, a register 21 is reset and a zero output is applied to a D-A converter 3. Outputs more than the level are applied to all OR circuits of a gate circuit 7 to bring the gates high in the level. All switches 41, 42 of a switching circuit 4 are turned on, the content of all sample hold circuits 51, 52 is made to zero to obtain zero output.
申请公布号 JPS58107949(A) 申请公布日期 1983.06.27
申请号 JP19810207602 申请日期 1981.12.21
申请人 CHINO SEISAKUSHO:KK 发明人 YAMAMOTO SHINTAROU
分类号 G06F11/00;G06F3/05 主分类号 G06F11/00
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