| 摘要 |
PURPOSE:To decrease a steady-state phase error, by comparing the phase of inputs to a phase comparator, outputting the result of comparison in rectangular wave and summing the integration of the wave to a VCO control voltage of a phase locked loop. CONSTITUTION:The 1st phase comparator PC1, a low pass filter LPF, a VCO, and a frequency divider DV constitute a conventional phase comparator. Further, the 2nd phase comparator PC2, an integrator INT, and an adder ADD are added, and when an output of the frequency divider DV is fluctuated in a slight phase due to an input signal, ''0'', ''1'' are outputted alternately, a prescribed output is given at the integrator INT, and the output is summed to a normal VCO control voltage, allowing to compensate the steady-state phase delay of the output of VCO. |
