| 摘要 |
PURPOSE:To control the priority with less hardware and in a single timing, by forming the priority circuit with a circuit forcedly resetting the content of an FF where the priority is low. CONSTITUTION:When request signals RQa1, RQb2 are set in hold FFs 31a, 32b in the same timing, since a gate of a cause transition determining circuit 101 operated at the time moving to service FFs 33a, 33b is opened, the content is smoothly moved. Based on the output of the FF33b set earlier, a bus request signal BUSREQ is made enable and the gate of the circuit 101 is closed at the same time. Even if the FFs 31a, 32b are set momentarily, the shift to the FF33b is inhibited. Further, based on a reset circuit 102 of low priority, the FF33b of the lower priority is set forcedly. |
