发明名称 MULTI-PROCESSOR SYSTEM
摘要 <p>PURPOSE:To simplify the system constitution and to attain high speed data processing, by connecting plural CPUs with a data bus and a control line, and feeding a clock signal in common to the CPUs. CONSTITUTION:Plural computer-use CPUs 4, 5..., a control use CPU1, are connected with a data bus 3 and control lines 4a, 4b, 5a, and 5b, and a clock signal is given to the CPUs 4, 5... and the CPU1 from an oscillator 6. Data are given to the CPU1 from external input/output port 2, and the CPUs 4, 5... compute the processing routine to be executed based on the data. The CPU1 transmits a start signal to the control lines 4a, 5a and the data corresponding to the processing routine to the CPUs 4, 5 via the data bus 3. The constitution of the multi-processor system is simplified and high speed data processing is performed.</p>
申请公布号 JPS58106650(A) 申请公布日期 1983.06.25
申请号 JP19810205945 申请日期 1981.12.18
申请人 NINTENDOU KK 发明人 KANEOKA YUKIO;MURAKUNAI KAGETSUGU
分类号 G06F15/16;G06F15/177;(IPC1-7):06F15/16 主分类号 G06F15/16
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