| 摘要 |
PURPOSE:To assign a specific address to each rack, by connecting a required upper-order digit of an address bus leading to a CPU one after another via an operating circuit provided in each latch, and providing a switching setter of an operation data for each rack. CONSTITUTION:An input circuit to fetch an input signal from an external sensor or the like, an output circuit to drive an external load device and a user's program memory are provided. Address data input terminals T3-T5 are connected to upper-order three lines A03-A05 of (9-3) [=6] address lines A00- A05 leading to an address data transmission terminal of a CPU unit when the rack is used as the 1st stage rack. When this rack is used for the rack for the next and succeeding stages, the terminals are connected to address data transmission terminals T3'-T5' of each preceding stage rack. The terminals T3'- T5' transmit numerical data corresponding to the result of operation of an operation circuit 9 to the input and output rack of the post stages. |
