| 摘要 |
PURPOSE:To make an economical constitution possible without requiring a ultrahigh-speed circuit, by outputting parallel data selectively after serial input data is converted to n-bit parallel data. CONSTITUTION:In respect to data DATA-IP inputted to the first register circuit 221, 13 continuous bits are read into stages 1-13 of the register circuit 221 and are read into stages 1'-13' of the second register circuit 222 as parallel data. One prescribed bit is selected from this parallel data in a selecting circuit 23 by a control signal CONT corresponding to the count number of a frequency dividing circuit 212 and is inputted to an output register circuit 24, and an output data string DAT-OP is outputted as a sampling frequency 4.fSC. |
