| 摘要 |
PURPOSE:To prevent occurrence of errors caused by noise, etc., by performing the slice level control and clock phase control on the data sampling when the framing code cannot be detected correctly for a number of time which exceeds a prescribed value. CONSTITUTION:Multiplex character signals from a terminal 31 are inputted into a serial-parallel converting circuit 33 through a slicing circuit 32, and outputted after they are converted into parallel signals by the sampling pulse from a divider 38. The sampling pulse is obtained when colck signals obtained through a chrominance subcarrier reproducing circuit 34, a multiplying circuit 35, and a delay circuit 36 are phase-selected by a data selector 37. A shift register 44 accumulates clock line codes and framing codes based on various timing signals of a sampling signal generating circuit 41 and input them into a microcomputer 47. When the framing code does not show a prescribed code continuously for a fixed number of times, the computer 47 refers the line code and controls the slice level of the slicing circuit 32 and the phase selecting position of the data selector 37. |
