| 摘要 |
PURPOSE:To perform a process with just an access to the consecutive input and output to a storage region, by using a register which advances stepwise the address information of a CPU and a means which controls the above-mentioned advancing and a consecutive memory access action. CONSTITUTION:When a consecutive read mode is designated, the read data is set to a data register 11 by a signal RCLK and then transferred to a CPU. When the first transfer of the read data is over, an end signal R/WEND is delivered from a controller 4. Then +1 is given to the contents of a counter 5 and an address register 8. The counter 5 sets an output signal line 21 at ''0'' when it receives two shots of clock signals. The signal R/WEND restarts the controller 4 through a gate 7. Thus the 2nd reading is carried out. |
