| 摘要 |
PURPOSE:To ensure a high-speed access without adding any address at all, by having a cascade connection among memory circuits, writing the data to be stored from the end of one side and then shifting successively the hitherto data every time the data is written. CONSTITUTION:When the write indicating signal W is applied from outside of a memory device, a control circuit 5 delivers the signal IN to indicate the writing of data to the memory parts 1 and 2 and then to a register 4. Thus the parts 1 and 2 and the register 4 fetch the data given from the front stage by the signal IN. When the data read indicating signal R is supplied to the circuit 5 from outside of the memory device, a comparator 3 compares the data line DOUT1 delivered from the memory part 1 with the data line D2 and then delivers the signal C to the circuit 5 when the coincidence is obtained. The circuit 5 delivers the signal OUT to urge the output of the deliver. Then the signal OUT is supplied, the memory part 2 delivers its own contents to a bus B1 through a data line D1. |
