发明名称 MEMORY CONTROLLER
摘要 PURPOSE:To assure a memory output data without using any exclusive buffer memory, by providing a small number of converting circuits. CONSTITUTION:A memory device 1 sets the end signal 6 at ''1'' and at the same time delivers the memory output data 9 when the request signal 5 is set at ''1'' with nonrefresh cycle. A memory access control circuit 2 sets the signal 5 at 1 and then sets the refresh detecting signal 8 at ''0'' in case the signal 6 is set at ''1'' after a prescribed time elapses. A converting circuit 3 feeds the data 9 direct ly to a processor 4 in the form of the output data 10 of the circuit 3 in case the signal 8 is set at ''0''. The data 9 is converted into a data pattern of NOOP (NO-OPERATION) of a microprogram instruction to be delivered to the processor 4 while the signal 8 is set at ''1''. In such a way, the data can be assured in a refresh cycle mode.
申请公布号 JPS58105484(A) 申请公布日期 1983.06.23
申请号 JP19810201601 申请日期 1981.12.16
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK 发明人 USAMI NAGATOSHI;NAKAMURA KAZUNORI
分类号 G11C11/00;G11C11/406 主分类号 G11C11/00
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