发明名称 UP/DOWN COUNTER
摘要 PURPOSE:To count up/down from an optional digit to fix the output of the optional digit by providing a counting up/down circuit with a means for controlling counting up/down and a means for fixing the output of a specific output bit. CONSTITUTION:Output signals from lower digits are inputted to terminals 102- 105 respectively. OR gates 120-123 find OR between the signals inputted to the terminals 106-109 and digit switching signals inputted to terminals 102-105 respectively. Thus signals outputted from the lower stages are selected to count up an optional digit. If ''1'' is set to an enable terminal 110, a signal inputted to a counting up input terminal 101 is directly outputted from an AND gate 129 to an OR gate 128. In case of counting down, counting down from an optional digit can be executed in accordance with a pulse inputted to a counting down input terminal 119. If ''0'' is set to the terminal 110, the output of the up/down counter can be held.
申请公布号 JPS58105629(A) 申请公布日期 1983.06.23
申请号 JP19810203546 申请日期 1981.12.18
申请人 HITACHI SEISAKUSHO KK 发明人 ARITA SETSUO
分类号 H03K23/00;H03K21/02 主分类号 H03K23/00
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