发明名称 SATURATED TYPE LOGICAL CIRCUIT
摘要 PURPOSE:To attain high-speed operation of a saturated type logical circuit, by improving an active pull-down circuit. CONSTITUTION:A saturated logical circuit is formed with a PNP input transistor (TR)Q1 connected to a power supply via an emitter resistor R1, a level shift TRQ2, a phase split stage TRQ3, and a common emitter output TRQ4. The emitter of TRQ7 the base of which is connected to the collector of the level shift TRQ2 via a resistor R3, is grounded, the collector is connected to the base of the output TRQ4 via a resistor R8, and the anode and cathode of a diode D2 are connected between the base of the TRQ7 and the collector of the PNP input TRQ1, and the collector of the PNP input TRQ1 is grounded via a resistor R4. The collector potential of the level shift TRQ2 is detected, allowing to interrupt/ conduct the TRQ7 in conducting/interrupting the output TRQ4.
申请公布号 JPS58104532(A) 申请公布日期 1983.06.22
申请号 JP19810202851 申请日期 1981.12.16
申请人 NIPPON DENKI KK 发明人 KIYOZUKA NOBORU;MORI SUSUMU
分类号 H03K19/088;H03K19/013 主分类号 H03K19/088
代理机构 代理人
主权项
地址