发明名称 SIGNAL DETECTION CIRCUIT AND PEAK HOLD CIRCUIT APPLYING SAID SIGNAL DETECTION CIRCUIT
摘要 PURPOSE:To detect the intermission of a signal after a prescribed time independently of a signal level of an input signal after the intermission of the signal by providing two peak hold means having a different holding time so as to detect the difference of output levels. CONSTITUTION:A holding capacitor C1(C2) and a constant current source i1(i2) are connected respectively to a collector of a transistor (TR) T1(T2) to constitute the two peak hold means P, Q. In providing a difference to a holding time while the capacitance of the capacitor C1 is selected to 1000pF And the capacitance of the capacitor C2 is selected to 5000pF, a comparator 3 is operative at 1 usec after an input signal to the peak hold circuits is intermitted. Thus, a current is given rapidly to the capacitors C1, C2 to bring the output of the peak hold circuits rapidly to the initial state. Thus, the peak hold circuit sP,Q are reset at the same time.
申请公布号 JPS62286312(A) 申请公布日期 1987.12.12
申请号 JP19860130983 申请日期 1986.06.05
申请人 SUMITOMO ELECTRIC IND LTD 发明人 FUKUOKA TAKASHI
分类号 H03K5/19;H03K5/153;H04B17/00;H04L25/02 主分类号 H03K5/19
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