发明名称 DETECTING CIRCUIT FOR ORDER OF SIGNAL GENERATION
摘要 PURPOSE:To simplify a circuit constitution and to facilitate changing a detecting pattern, by constituting the circuit only with a storage device and a counter, and detecting it by a prescribed pattern that plural input signals are generated in a prescribed order. CONSTITUTION:A trigger circuit consists of a storage device 34 and N-bit counters 36 and 38. When outputs A, B, and C of a word recognizer are inputted to address signal input terminals A2-A4 of the storage device 34 in order, outputs from output terminals D0-D2 are all 0 in the initial state. When the signal A is generated, only the output terminal D0 outputs a signal, and the counter 36 outputs ''1'' to a terminal A0, and the state is held. When the signal B is generated in this state, the output terminal D1 outputs a signal, and the counter 38 outputs ''1'' to a terminal A1, and the state is held. When the signal C is generated in this state, the output terminal D2 outputs a signal. The signal of the terminal D2 is applied to a fetch memory through an output terminal 40 and a fetch control circuit to stop the signal fetch of the memory, thereby storing a desired part of input signals.
申请公布号 JPS58103045(A) 申请公布日期 1983.06.18
申请号 JP19810201784 申请日期 1981.12.15
申请人 SONII TEKUTORONIKUSU KK 发明人 TAKITA KENTAROU
分类号 G01R13/28;G01R31/28;G01R31/317;G01R31/3183;G06F11/22;H03K5/26 主分类号 G01R13/28
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