| 摘要 |
PURPOSE:To obtain a device which causes no malfunction even if a clock pulse between blocks is delayed by inserting a flip-flop which is triggered by an inverted clock pulse at the division point of blocks of a shift register. CONSTITUTION:A shift register is divided into plural blocks and flip-flops which are triggered by an inverted clock pulse are inserted at division points. For example, an input signal (a) from an input terminal 5 is inputted to a terminal D of an FF1 and a clock pulse phia1 from an input terminal 6 is inputted to a terminal T to read data at the leading edge of the clock pulse and then store it. Then, the output signal (b) of the FF1 is inputted to a terminal D of an FF2 and the clock pulse phia1 is inputted to a terminal T of the FF2 to send its output signal (c) to an FF2a. Then, the output signal (c) of the FF2 is inputted to a terminal D of the FF2a and an inverted clock pulse phib1 sent out through an inverter 9 is inputted to a terminal T to trigger the FF2a. |
