发明名称 DATE TRANSMISSION PROCESSOR
摘要 PURPOSE:To reduce errors in data transmission and to decrease the transmission time, by providing a humming correction code and a parity bit to data to be transmitted in a specific method. CONSTITUTION:In storing data of 16 bits to an RAM of 4-bit unit, for example, data D1-D11 in order to bits of the RAM except a parity p are humming correction codes H0-H3 and the H0-H3 and O and obtained and added. In obtaining the H0 first, the bit test for D1, D2, D4, D5, D7, D9, D11 is done in accordance with the A and an even parity is obtained by adding the H0. Similarly, the H1, H2, H3 are obtained in accordance with the B,C,D. The parity of P is obtained by taking the bits of D1-D11, H0-H3, and P as an even number, for example. The information of D11 from the P thus obtained is transmitted from the RAM to external circuitry bit-serially in the order of Y0(P, H0, H1, D1), Y1(H2, D2, D3, D4), Y2(H3, D5, D6, D7) and Y3 (D8, D9, D10, D11).
申请公布号 JPS58101539(A) 申请公布日期 1983.06.16
申请号 JP19810200647 申请日期 1981.12.11
申请人 SONY KK 发明人 OSAKABE YOSHIO
分类号 H04L1/00;G06F11/10;H03M13/19 主分类号 H04L1/00
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