| 摘要 |
<p>PURPOSE:To perform transmission without decreasing amplitude, by providing a delay circuit on the data line of a logic circuit, and fixing the length of a clock line so as to maximize the amplitude of a clock signal in the logic circuit. CONSTITUTION:By providing a delay part 4 on a data line 5, and assuming the wavelength of the clock signal as lambda0, the maximum point of the amplitude exists at a part being multiplied by the integer of the half-wave length of lambda0. Therefore, by stipulating the length of a clock line 6 as nlambda0/2, the transmission can be obtained without attenuating the amplitude of a clock signal CLK.</p> |
