发明名称 Circuit arrangement for calibrating signalling lines
摘要 The circuit arrangement essentially consists of a window discriminator which compares the line voltage of a signalling line with predetermined voltage values and outputs an alarm signal when the line voltage deviates from a predetermined tolerance window. This tolerance window is narrowed for the calibration process by means of a line key, which also results in an alarm signal when the signalling line is inadequately calibrated. The operation of the line key has the effect that this alarm signal is not forwarded and an indicating element is switched on via a clock generator until the line calibration has been correctly performed by means of a calibration resistance. The indicating element is then extinguished and the line key can be reset to its original position.
申请公布号 DE3148277(A1) 申请公布日期 1983.06.16
申请号 DE19813148277 申请日期 1981.12.05
申请人 FRIEDRICH MERK-TELEFONBAU GMBH 发明人 ARNDT,KURT,DIPL.-ING.;THEILIG,FRANK
分类号 G08B29/02;(IPC1-7):G08B29/00 主分类号 G08B29/02
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