发明名称 CHATTERING PREVENTING CIRCUIT
摘要 PURPOSE:To prevent a full electronic timepiece from malfunction owing to a noise in alarm sounding and to take an IC test easily in a short time by inserting a chatter eliminating circuit even for a test signal. CONSTITUTION:A chattering eliminating circuit 1-4 is inserted for a test input signal 8, and its output signal is used to perform control over whether a mode input signal 2, selection input signal 4, and set input signals 6 are passed through chattering eliminating circuits 1-1, 1-2, and 1-3 or not respectively. During alarm sounding, if noises are induced on signal lines for said signals 2, 4, and 6, and a test signal 8, the noise of the test signal 8 is removed by the chattering elimiating circuit 104 and noise is cut off in the output signal 10. Theefore, noises induced in the signals 2, 4, and 6 are cut off through control logical gates 9-1, 9-2, and 9-3 in normal operation.
申请公布号 JPS58100776(A) 申请公布日期 1983.06.15
申请号 JP19810199801 申请日期 1981.12.11
申请人 SUWA SEIKOSHA KK 发明人 YAMADA ATSUSHI
分类号 G04D7/00;G04G21/00;G04G99/00 主分类号 G04D7/00
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