Integrated process for manufacturing logical circuits comprising at least one field effect transistor having a low threshold voltage and a saturation resistor, and logical circuit made by that process.

摘要

1. Method for the collective fabrication of logic circuits each comprising at least one field-effect transistor of low threshold voltage and a saturable resistor, comprising the following steps : a) fabrication of a semiconductor wafer comprising on an insulating substrate (1) an active layer (2) of thickness at least equal to a predetermined value ; b) erosion of the active layer (2) by an electrochemical or ion etching method to reduce the thickness of said layer up to a value a1 determined by electronic means ; c) isolation of the wafer zones respectively intended to receive a component of the logic circuit by mesa etching or by ion implantation of insulating barriers (41, 42 and 43) ; d) deposition of ohmic contacts of the transistors (53 and 54) and of the saturable resistors (51 and 52) ; e) simultaneous formation of Schottky contacts (62), deposited between the ohmic contacts of the saturable resistors and of metallic depositions (61, 63, 64 and 65) which cover the ohmic contacts ; f) deposition of metallizations (84) connecting one of the ohmic contacts of each saturable resistor to the Schottky contact formed in step (e) ; g) production of the trough (81) of each field-effect transistor of low threshold voltage by ion erosion to a depth a0 calculated in dependence upon the thickness a1 measured in step (b) ; h) deposition of Schottky contacts (82) at the bottom of the troughs formed in step (g) ; i) production of the interconnections and connections (83 and 85) belonging to each logic circuit.