发明名称 CMOS-RAM
摘要 PURPOSE:To protect the memory and reduce the electric power consumption at the time of backup of the power source without specifying the output controlling function, by controlling the FET forming an address buffer by the power source detecting output. CONSTITUTION:An address buffer of an RAM memory array of an matrix array constituted by a CMOS is formed by a CMOS NOR circuit composed of an n type MOSFET Q1, a p type MOSFET Q2, an n type MOSFET Q3, a p type MOSFET Q4, etc. The FETs Q3 and Q4 connected in parallel with each other are controlled through an n type MOSFET Q5 and invertors IV2 and IV3 which are controlled by the voltage detecting output. Therefore, the holding operation of the memory at the time of backup mode where the supply voltage is low is guaranteed, because the FETs Q4 and Q5 are set to the ''off'' and ''on'' conditions, respectively, and, at the same time, the power consumption is not increased, because the response to the noise from an external terminal AXi is inhibited. Therefore, protection of the memory and reduction in the electric power consumption at the time of backup of the power source can be realized without specifying the output controlling function.
申请公布号 JPS58100290(A) 申请公布日期 1983.06.14
申请号 JP19810198546 申请日期 1981.12.11
申请人 HITACHI SEISAKUSHO KK 发明人 UCHIBORI KIYOBUMI
分类号 G11C11/41;G11C8/06;G11C11/413 主分类号 G11C11/41
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