| 摘要 |
PURPOSE:To shorten detection time by detecting the timing of a complement code signal in one block and detecting a frame synchronizing signal on the basis of the complement code signal. CONSTITUTION:A frame synchronizing signal detector consists of a bit synchronizing circuit 1, block synchronizing circuit 2, and frame synchronizing circuit 3. When the block synchronizing circuit 2 obtains the timing of a complement code signal, a frame synchronizing signal is at a predetermined position relative to the complement code signal, so the frame synchronizing circuit 3 obtain a signal to be transmitted at time delayed behind the timing of the complement code signal by an integral multiple of some determined clock period; and the irregularity of the obtained signal is collated with an array of predetermined frame synchronizing signals and when their coincidence is obtained, it is evident that the frame synchronizing signal is transmitted at the timing of the obtained signal, thus obtaining the frame synchronizing signal. |
