| 摘要 |
PURPOSE:To decrease the number of memory stages by dispersedly inserting additional codes except at one bit before and behind the insertion position of a code mc without succession. CONSTITUTION:The number ms of memory stages necessary for speed conversion and insertion and deletion of additional information is mjs+mss+mDs, where mjs is a value while the probability of a memory slip and transmission line jitters are considered, mDs is a value determined by the jitters due to unnecessary pulse insertion such as staff synchronization, and mss is a value relating directly to frame constitution. When pieces of additional information are inserted successively, the number of memory stages increases. For this purpose, one frame consists of, for example a 6-bit information pulse 1, 1-bit information pulse 5, 4-bit information pulse 6, 1C pulses 4-1, 4-2, and 4-3, and additional information pulse 3. Namely, the memory stage number is decreased so that an additional information pulse does not succeed to the 1C pulse. |
