发明名称 TESTING SYSTEM FOR IC MEMORY
摘要 PURPOSE:To easily find out a faulty memory cell by a method wherein data coded reversely to data written beforehand in a read address position are given to IC by a write pulse having a pulse width of 1/8-1/2 of a normal write width. CONSTITUTION:In a write cycle, a test data pattern selected by a pattern generator 13 is sent out to a buffer register 14, an NOT circuit 16 and a switching circuit 17. In a read cycle, a reverse pattern of test data which is inverted by the NOT circuit 16 and thus coded reversely to the test data pattern is sent out to an IC memory 10 to be tested with a pulse width of 1/8-1/2 of a normal write pulse width by the switching circuit 17, before it is sent to a read strobe position. Then, a data output obtained by adding a strobe is compared and collated with the test data pattern sent out from said buffer register 14 by a comparison circuit 15. When the reverse pattern of the test data is written on said occasion, no coincidence is obtained between the two data because of the presence of a faulty memory cell, and thereby a non-coincidence information indicating the presence of the faulty memory cell can be obtained.
申请公布号 JPS5896260(A) 申请公布日期 1983.06.08
申请号 JP19810195292 申请日期 1981.12.04
申请人 FUJITSU KK 发明人 KOBIYAMA KIYOYUKI
分类号 G01R31/28;G11C29/00;G11C29/08;G11C29/50 主分类号 G01R31/28
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