发明名称 |
Error prevention in TTL circuits. |
摘要 |
<p>A TTL circuit, controllable by an input signal so that when the circuit is in a normal steady-state operating condition it delivers an output signal which will undergo a predetermined change in response to a predetermined change in the input signal, includes error prevention circuitry (DS1-DSn) for preventing such response to said change in the input signal if a power supply voltage (Vcc) applied to the circuit is at a subnormal value, below a threshold value imposed by the error prevention circuitry, for example during start-up of the device.</p> |
申请公布号 |
EP0080874(A2) |
申请公布日期 |
1983.06.08 |
申请号 |
EP19820306311 |
申请日期 |
1982.11.26 |
申请人 |
FUJITSU LIMITED |
发明人 |
SUZUKI, HIROKAZU;AKIYAMA, TAKEHIRO FUJITSU DAI-1 ICHIGAO-RYO |
分类号 |
H03K19/003;H03K17/22;H03K19/088;(IPC1-7):03K19/003;03K17/22 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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