发明名称 |
Hardware scheduler/dispatcher for data processing system |
摘要 |
A general-purpose, tightly-coupled multiprocessing system wherein processors share a common memory. A hardware-recognizable object (a process object) in memory stores access descriptors for controlling the type and extent of access to objects associated with a process, including one describing a buffered port. Another hardware-recognizable object (a processor object) associated with an executing process, stores access descriptors for controlling the type and extent of access to objects associated with a processor, including one describing a dispatching port. Task-dispatching functions are accomplished by hardware-controlled queuing mechanisms at the buffered ports and dispatching ports. These mechanisms allow different processes to communicate with each other and bind ready-to-run processes with available processors for execution.
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申请公布号 |
US4387427(A) |
申请公布日期 |
1983.06.07 |
申请号 |
US19800197655 |
申请日期 |
1980.10.16 |
申请人 |
INTEL CORPORATION |
发明人 |
COX, GEORGE W.;RATTNER, JUSTIN R. |
分类号 |
G06F9/46;G06F9/48;(IPC1-7):G06F15/16 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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