DIGITAL SIGNAL PROCESSOR

摘要

PURPOSE:To decrease the signal transfer time, by performing a parallel transfer of data between a digital signal processor and an analog device and at the same time converting the number of bits for the transfer data. CONSTITUTION:A transfer data of a data bus line of a digital signal processor 50 is fetched into an input register 44 by the signal of an instruction line 23 supplied from an instruction memory 16 and the signal of a timing line 21 supplied from a timing producing circuit 18. The data fetched into the register 44 is supplied to a bit compressor 32 as an output signal 55 of an input register to convert a data of 16 bits into data of 8 bits. Thus the parallel data of 8 bits is delivered from an output control circuit 47. While the data supplied from a data input terminal 57 is supplied to a bit expander 37 via an input controlling circuit 40 and with the signal applied to an input control terminal 58 synchronously with said data. Then this data is transferred to the bus line 25 in the form of a parallel data of 16 bits. As a result, no serial-parallel inversion is required.