| 摘要 |
PURPOSE:To attain normal operation even if access cycle speeds up, by sufficiently ensuring a setup time and hold time at a reception side, through the widening of the width of transmission data at a transmission side and provision of them to a plurality of data reception sections. CONSTITUTION:A start signal GO and address information AD are transferred at the same time and a write data WD are transferred with a delay of 1gamma from the GO and AD. GO' and AD' are generated with a delay of 1gamma than the GO, AD. The WD is inputted to a register 3 set with a signal CYC. When the CYC is 0, the WD is set to a register 3-1 and when 1, it is set to a register 3-2. Thus, the WD transmitted at a width of 1gamma is extended into 2gamma as two write data EWD and OWD, which are transferred from the logical section to the storage section via buses 13 and 14 respectively. Either EWD or OWD is selected at a multiplexer 25 at one block of the storage sectin and set to a register 6 with a write information set clock signal WCLKO. |
