| 摘要 |
A chip-level power combiner comprises plural amplifier devices, a power divider, and a power combiner. The power divider and the power combiner are disposed in mirror-image fashion. Each divider/combiner comprises a first divider/combiner section having plural branch transmission lines cascading from/to a main transmission line, and a second divider/combiner section having plural feeder transmission lines cascading from/to each branch of the transmission line. Each of the branch and feeder transmission lines has an isolation resistor interposed between adjacent lines, and the feeder transmission lines are tapered.
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