| 摘要 |
PURPOSE:To simplify bipolar-CMOS structure, and to shrink chip size with the simplification by connecting a P<-> well to an isolation P<+> layer and directly grounding the source electrode of an N channel MOSFET to low potential. CONSTITUTION:One side section of the P<-> well 5 to which the N channel MOSFET is shaped is stacked to the isolation P<+> layer 4, and N<+> regions 8, 8 as source-drain are formed to the surfce of the P well, and a P<+> layer 9 in shape that is stacked to one part of one N<+> region (source) is extended up to the end of the P well 5 and stacked to the isolation P<+> layer. The surfaces of the N<+> regions and the P<+> layer 9 are mutually short-circuited by a common Al electrode. An N<+> region 12 as the collect of the NPN bipolar transistor, a P region 13 as a base and an N<+> region 14 as an emitter are formed to the surface of another N<-> layer 11 isolated by the isolation P<+> layer 4. |
